000			04712nam a22002295i 4500
999			_c32328 _d32328
010			_a 2017942739
020			_a9783319072357
020			_a3319072358
082			_a621.3815 SY ST
245	0	0	_aSystem reduction for nanoscale IC design _cEdited by Peter Benner
260			_aNew York, NY : _bSpringer Berlin Heidelberg, _c2017.
300			_axi, 197 p. : _bill. (some col.) ; _c25 cm.
490			_aMathematics in industry ; _v20.
520			_aThis book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.
650			_aIntegrated circuits _vDesign and construction _99823
650			_aNanoelectronics _vDesign and construction _99824
856			_uhttps://uowd.box.com/s/6ba363cdv9zmjtpr68mlm8ovfv36swpw _zLocation Map