Real world FPGA design with Verilog
By: Coffman, Ken
Material type:
BookPublisher: Upper Saddle River, NJ : Prentice Hall PTR, c2000.Description: xv, 291 p. : ill. ; 25 cm.ISBN: 978-0130998514Program: ECTE433Other title: FPGA design with Verilog.Subject(s): Field programmable gate arrays -- Computer-aided design | Verilog (Computer hardware description language) | FPGADDC classification: 621.39/5 Online resources: Location Map | Item type | Home library | Call number | Status | Date due | Barcode | Item holds | Course reserves |
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| REGULAR | University of Wollongong in Dubai Main Collection | 621.395 CO RE (Browse shelf) | Available | T0054884 |
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| 621.392 SA FU Fundamentals of digital and computer design with VHDL / | 621.395 BO PR Programmable logic controllers / | 621.395 CO RA Rapid system prototyping with FPGAs / | 621.395 CO RE Real world FPGA design with Verilog | 621.395 DA DI Digital design lab manual / | 621.395 DE DI Digital systems from logic gates to processors | 621.395 FL DI Digital fundamentals / |
Other Titles: FPGA design with Verilog
Includes bibliographical references (p. 285) and index.
1. Verilog Design in the Real World. Trivial Overheat Detector Example. Synthesizable Verilog Elements. Verilog Hierarchy. Built-In Logic Primitives. Latches and Flipflops. Blocking and Nonblocking Assignments. Miscellaneous Verilog Syntax Items. 2. Digital Design Strategies and Techniques. Design Processing Steps. Analog Building Blocks for Digital Primitives. Using a LUT to Implement Logic Functions. Discussion of Design Processing Steps. Synchronous Logic Rules. Clocking Strategies. Logic Minimization. What Does the Synthesizer Do? Area/Delay Optimization. 3. A Digital Circuit Toolbox. Verilog Hierarchy Revisited. Tristate Signals and Busses. Bidirectional Busses. Priority Encoders. Area/Speed Optimization in Synthesis. Trade-off Between Operating Speed and Latency. Delays in FPGA Logic Elements. State Machines. Adders. Subtractors. Multipliers. 4. More Digital Circuits: Counters, RAMs, and FIFOs. Ripple Counters. Johnson Counters. Linear Feedback Shift Registers. Cyclic Redundancy Checksums. ROM. RAM. FIFO Notes. 5. Verilog Test Fixtures. Compiler Directives. Automated Testing. 6. Real World Design: Tools, Techniques, and Trade-offs. Compiling with LeonardoSpectrum. Complete Design Flow, 8-Bit Equality Comparator. 8-Bit Equality Comparator with Hierarchy. Optimization Options In the Xilinx Environment. Mapping Options. Logic Level Timing Report/Post Layout Timing Report. VHDL/Verilog Simulation Options. Other Design Manager Tools. 7. A Look at Competing Architectures. Factors that Determine Integrated Circuit Pricing. FPGA Device Design. FPGA Technology Selection Checklist. Xilinx FPGA Architectures. Altera CPLD Architectures. 8. Libraries, Reusable Modules, and IP. Keys to Increased Productivity. Library Elements. Structural Coding Style. A Small Diversion to Compare a Schematic to a Verilog Design. Using LogiBLOX Module Generator. Design Reuse, Reusing Your Own Code. Buying IP Designs. Summing Up. 9. Designing for ASIC Conversion. HardWire Devices. Semicustom Devices. Design Rules for ASIC Conversion. Synchronous Design Rules. Oscillators. Delay Lines. The Language of Test. Print-on-Change Test Vectors. Afterword-A Look into the Future. Resources. Glossary and Acronyms. Bibliography. Index. The Author
CD-ROM contains working demo and student versions of Prism Editor and Simucad's Silos III simulator, EMATH (a collection of more than 300 key electrical engineering formulas) and electronic copies of all the Verilog code from the book.
ECTE433