Includes bibliographical references and index.

Logic synthesis is an essential part of the modern digital IC design process in semi–conductor industry. This book discusses a logic synthesis technique called “rewiring” and its latest technical advancement in term of rewirability. Rewiring technique has surfaced in academic research since 1993 and there is currently no book available on the market which systematically and comprehensively discusses this rewiring technology. The authors cover logic transformation techniques with concentration on rewiring. For many decades, the effect of wiring on logic structures has been ignored due to an ideal view of wires and their negligible role in the circuit performance. However in today’s semiconductor technology wiring is the major player in circuit performance degeneration and logic synthesis engines can be improved to deal with this through wire–based transformations. This book introduces the automatic test pattern generation (ATPG)–based rewiring techniques, which are recently active in the realm of logic synthesis/verification of VLSI/SOC designs.