Preface; Contents; 1 Model Order Reduction of Integrated Circuitsin Electrical Networks; 1.1 Introduction; 1.2 Basic Models; 1.2.1 Coupling; 1.3 Simulation of the Full System; 1.3.1 Standard Galerkin Finite Element Approach; 1.3.2 Mixed Finite Element Approach; 1.4 Model Order Reduction Using POD; 1.4.1 Numerical Investigation; 1.4.2 Numerical Investigation, Position of the Semiconductor in the Network; 1.4.3 MOR for the Nonlinearity with DEIM; 1.4.4 Numerical Implementation and Results with DEIM; 1.5 Residual-Based Sampling; 1.5.1 Numerical Investigation for Residual Based Sampling. 1.6 PABTEC Combined with POD MOR1.6.1 Decoupling; 1.6.2 Model Reduction Approach; 1.6.3 Numerical Experiments; References; 2 Element-Based Model Reduction in Circuit Simulation; 2.1 Introduction; 2.2 Circuit Equations; 2.2.1 Graph-Theoretic Concepts; 2.2.2 Modified Nodal Analysis and Modified Loop Analysis; 2.2.3 Linear RLC Circuits; 2.2.3.1 Passivity; 2.2.3.2 Stability; 2.2.3.3 Reciprocity; 2.3 Model Reduction of Linear Circuits; 2.3.1 Balanced Truncation for RLC Circuits; 2.3.2 Balanced Truncation for RC Circuits; 2.3.2.1 RCI Circuits; 2.3.2.2 RCV Circuits; 2.3.2.3 RCIV Circuits. 2.3.3 Numerical Aspects2.4 Model Reduction of Nonlinear Circuits; 2.5 Solving Matrix Equations; 2.5.1 ADI Method for Projected Lyapunov Equations; 2.5.2 Newton's Method for Projected Riccati Equations; 2.6 MATLAB Toolbox PABTEC; 2.7 Numerical Examples; References; 3 Reduced Representation of Power Grid Models; 3.1 Introduction; 3.2 System Description; 3.2.1 Basic Definitions; 3.2.2 Benchmark Systems; 3.2.2.1 A Test Circuit Example; 3.2.2.2 Linear Subdomain for Non-linear Electro-Quasistatic Field Simulations; 3.3 Terminal Reduction Approaches; 3.3.1 (E)SVDMOR; 3.3.2 TermMerg. 3.3.2.1 The k-Means Clustering Algorithm3.3.2.2 The Reduction Step; 3.3.3 SparseRC; 3.3.3.1 MOR via Graph Partitioning and EMMP; 3.3.4 MOR for Many Terminals via Interpolation; 3.3.4.1 Tangential Interpolation and the Loewner Concept; 3.4 ESVDMOR in Detail; 3.4.1 Stability, Passivity, Reciprocity; 3.4.1.1 Stability; 3.4.1.2 Passivity; 3.4.1.3 Reciprocity; 3.4.2 Error Analysis; 3.4.2.1 Particular Error Bounds; 3.4.2.2 Total ESVDMOR Error Bound; 3.4.3 Implementation Details; 3.4.3.1 The Implicitly Restarted Arnoldi Method; 3.4.3.2 The Jacobi-Davidson SVD Method; 3.4.3.3 Efficiency Issues. 3.4.3.4 Truncated SVD of the Input Response Moment Matrix MI3.4.3.5 Truncated SVD of the Output Response Moment Matrix MO; 3.5 Summary and Outlook; References; 4 Coupling of Numeric/Symbolic Reduction Methods for Generating Parametrized Models of NanoelectronicSystems; 4.1 Introduction; 4.1.1 Symbolic Modeling of Analog Circuits; 4.2 Hierarchical Modelling and Model Reduction; 4.2.1 Workflow for Subsystem Reductions; 4.2.2 Subsystem Sensitivities; 4.2.3 Subsystem Ranking; 4.2.4 Algorithm for Hierarchical Model Reduction; 4.3 Implementations; 4.4 Applications; 4.4.1 Differential Amplifier.

This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.